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hanbit hm d4m72d18g url:www.hbe.co.kr - 1 - hanbit electronics co.,ltd. rev. 1.0 (august.2002) general description the hmd4m72d18g is a 4 mx 72 bits dynamic ram high density memory module. the hmd4m72d18g consists of eight een cmos 4 mx4bits drams in soj/tsop ?? 400mil package s mounted on a 168 - pin glass - epoxy substrate. a 0.1 or 0.22uf decoupling capacitor is mounted on the printed circuit board for each dram. the hmd4m72d18 is a dual in - line memory module and is intended for mounting into 168 pin edge connector sockets features performance range w part identification hmd4m72d18g --- 4kcycles/64ms ref, gold plate lead w high - density 32 mbyte design w new jedec standard proposal without buffer w cas - before - ras refre sh capability w ras - only and hidden refresh capability w single + 5 0. 5 v power supply w timing w fast page mode operation . 50 n s access - 5 w lv ttl compatible inputs and outputs 60 n s access - 6 w fr4 - pcb design w packages w access times : 50, 60ns 168 - pin dimm d pin names pin name function pin name function pin name func tion a0 - a11 address input (4k ref) /ras0, /ras 2 row address strobe vss ground a0 - a12 address input (8k ref) /cas0 - /cas 7 column address strobe nc no connection /w 0,/w2 read/write enable scl serial clock vcc power (+ 5 v) /oe0,/oe2 output enable du don't use sda serial address /data i/o sa0 C sa2 address in eeprom cb0 - cb7 check bit dq0 - dq 63 data in/out speed t rac t cac t rc t hpc - 5 50ns 1 8 ns 90ns 35ns - 6 60ns 20ns 1 10 ns 40ns 32mbyte(4mx72) fast page mode 4k ref. 5v, dimm 168 pin part no. hm d4m72d18g
hanbit hm d4m72d18g url:www.hbe.co.kr - 2 - hanbit electronics co.,ltd. rev. 1.0 (august.2002) pin symbol pin symbol pin symbol pin symbol pin symbol pin symbol 1 vss 29 /cas1 57 dq18 85 vss 113 /cas5 141 dq50 2 dq0 30 /ras0 58 dq19 86 dq3 2 114 /ras1 142 dq51 3 dq1 31 /oe0 59 vcc 87 dq33 115 nc 143 vcc 4 dq2 32 vss 60 dq20 88 dq34 116 vss 144 dq52 5 dq3 33 a0 61 nc 89 dq35 117 a1 145 nc 6 vcc 34 a2 62 nc 90 vcc 118 a3 146 nc 7 dq4 35 a4 63 nc 91 dq36 119 a5 147 nc 8 dq5 36 a6 64 vss 9 2 dq37 120 a7 148 vss 9 dq6 37 a8 65 dq21 93 dq38 121 a9 149 dq53 10 dq7 38 a10 66 dq22 94 dq39 122 a11 150 dq54 11 dq8 39 nc 67 dq23 95 dq40 123 nc 151 dq55 12 vss 40 vcc 68 vss 96 vss 124 vcc 152 vss 13 dq9 41 vcc 69 dq24 97 dq41 125 nc 153 dq56 14 dq10 42 nc 70 dq25 98 dq42 126 nc 154 dq57 15 dq11 43 vss 71 dq26 99 dq43 127 vss 155 dq58 16 dq12 44 /oe2 72 dq27 100 dq44 128 nc 156 dq59 17 dq13 45 /ras2 73 vcc 101 dq45 129 /ras3 157 vcc 18 vcc 46 /cas2 74 dq28 102 vcc 130 /cas6 158 dq60 19 dq14 47 /cas3 75 dq29 103 dq46 131 /cas7 159 dq61 20 dq15 48 /w2 76 dq30 104 dq47 132 nc 160 dq62 21 cb0 49 vcc 77 dq31 105 cb4 133 vcc 161 dq63 22 cb1 50 nc 78 vss 106 cb5 134 nc 162 vss 23 vss 51 nc 79 nc 107 vss 135 nc 163 nc 24 nc 52 cb2 80 nc 108 nc 1 36 cb6 164 nc 25 nc 53 cb3 81 nc 109 nc 137 cb7 165 sa0 26 vcc 54 vss 82 sda 110 vcc 138 vss 166 sa1 27 /w0 55 dq16 83 scl 111 nc 139 dq48 167 sa2 28 /cas0 56 dq17 84 vcc 112 /cas4 140 dq49 168 vcc p in assi gnment
hanbit hm d4m72d18g url:www.hbe.co.kr - 3 - hanbit electronics co.,ltd. rev. 1.0 (august.2002) functional block dia gram 0.1uf or 0.22uf capacitor for each dram to all drams cb0 - 7 dq 0 - 63 vcc vs / cas dq0 - 3 /ras /oe /w a0 - a1 1 u 1 /cas dq4 - 7 /ras /oe /w a0 - a1 1 u 2 /cas dq 8 - 11 /ras /oe /w a0 - a1 1 u 3 /cas dq 12 - 15 /ras /oe /w a0 - a1 1 u 4 /cas dq1 6 - 19 /ras /oe /w a0 - a1 1 u 6 /cas dq 20 - 23 /ras /oe /w a0 - a1 1 u 7 /cas dq 24 - 27 /ras /oe /w a0 - a1 1 u 8 /cas dq 28 - 31 /ras /oe /w a0 - a1 1 u 9 /cas dq 32 - 35 /ras /oe /w a0 - a1 1 u 11 /cas dq 36 - 39 /ras /oe /w a0 - a1 1 u 12 /cas dq 40 - 43 /ras /oe /w a0 - a1 1 u 13 /cas dq 44 - 47 /ras /oe /w a0 - a1 1 u 14 /cas dq 48 - 51 /ras /oe /w a0 - a1 1 u1 5 /cas dq 52 - 55 /ras /oe /w a0 - a1 1 u1 6 /cas dq 56 - 59 /ras /oe /w a0 - a1 1 u 17 /cas dq 60 - 63 /ras /oe /w a0 - a1 1 u 18 /cas 4 /ras 2 /oe2 /cas5 /cas6 /cas7 /cas cb0 - 3 /ras /oe /w a0 - a1 1 /cas cb4 - 7 /ras /oe /w a0 - a1 1 u 5 u 15 /cas /ras0 /oe0 / cas /cas2 /cas3 /we0 /we2 a(0:11)
hanbit hm d4m72d18g url:www.hbe.co.kr - 4 - hanbit electronics co.,ltd. rev. 1.0 (august.2002) absolute maximum rat ings parameter symbol rating voltage on any pin relative to vss v in ,out - 0.5v to 4.6v voltage on vcc supply relative to vss vcc - 0.5v to 4.6v power dissipation p d 18 w storag e temperature t stg - 55 o c to 150 o c short circuit output current i os 50ma w permanent device damage may occur if " absolute maximum ratings" are exceeded. functional operation should be restricted to the conditions as detailed in the operational section s of this data sheet. exposure to absolute maximum rating conditions for extended periods may affect device reliability. recommended dc opera ting conditions ( voltage reference to v ss , t a =0 to 70 o c ) parameter symbol min typ . max unit supply vol tage vcc 4 . 5 5 . . 5 . 5 v ground vss 0 0 0 v input high voltage v ih 2. 4 - vcc+ 1 v input low voltage v il - 1 . 0 - 0.8 v dc and operating cha racteristics (recommended operating conditions unless otherwise noted) hmd4m72d18eg (4k ref) symbol speed mi n max units i cc1 - 5 - 6 - 1980 1800 ma ma i cc2 don't care - 18 ma i cc3 - 5 - 6 - 1980 1800 ma ma i cc4 - 5 - 6 - 1620 1440 m a ma i cc5 don't care - 9 ma i cc6 - 5 - 6 - 1980 1800 m a ma i cc7 i ccs l l 4500 3600 m a m a i cc1 : operating current * (/ras , /cas , addr ess cycling @t rc =min.) i cc2 : standby current ( /ras=/cas=v ih ) i cc3 : /ras only refresh current * ( /cas=v ih , /ras, address cycling @t rc =min )
hanbit hm d4m72d18g url:www.hbe.co.kr - 5 - hanbit electronics co.,ltd. rev. 1.0 (august.2002) i cc4 : fast page mode current * (/ras=v il , /cas, address cycling @t pc =min ) i cc5 : standby current (/ras=/cas=v cc - 0.2v ) i cc6 : /cas - before - /ras refresh current * (/ras and /cas cycling @t rc =min ) i il : input leakage current (any input 0v v in 4.5v, all other pins not under test = 0v) i ol : output leakage current (data out is disabled, 0v v out 3.3v v oh : out put high voltage level (i oh = - 2 ma ) v ol : output low voltage level (i ol = 2 ma ) * note: i cc1 , i cc3 , i cc4 and i cc6 are dependent on output loading and cycle rates. specified values are obtained with the output open. i cc is specified as an ave rage current. in i cc1 and i cc3 , address cad be changed maximum once while /ras=v il . in i cc4 , address can be changed maximum once within one page mode cycle. capacitance ( t a =25 o c, vcc = 5 v, f = 1mz ) description symbol min max units input capa citance (a0 - a1 1 ) c in1 - 20 pf input capacitance (/w 0, /w 1, / oe0, / oe2 ) c in2 - 20 pf input capacitance (/ras0 ,/ras2 ) c in3 - 73 pf input capacitance (/cas0 - /cas 7 ) c in4 - 20 pf input/output capacitance (dq0 - 63 ) c dq1 - 17 pf ac characteristics ( 0 o c t a 70 o c , vcc = 5 v 10%, see notes 1,2.) - 5 - 6 standard operation symbol min max min max unit random read or write cycle time t rc 8 4 104 ns read - modify - write cycle time t r w c 116 140 ns access time from /ras t rac 50 60 ns access time from /cas t cac 13 15 ns access time from column address t aa 25 30 ns /cas to output in low - z t clz 3 3 ns /oe to output in low - z t o lz 3 3 ns output buffer turn - off delay fro m /cas t off 3 13 3 13 ns transition time (rise and fall) t t 2 50 2 50 ns /ras precharge time t rp 30 40 ns /ras pulse width t ras 50 10k 60 10k ns /ras hold time t rsh 13 15 ns /cas hold time t csh 38 4 5 ns /cas pulse width t cas 8 10k 10 10k ns /ras to /cas delay time t rcd 20 37 20 45 ns
hanbit hm d4m72d18g url:www.hbe.co.kr - 6 - hanbit electronics co.,ltd. rev. 1.0 (august.2002) /ras to column address delay time t rad 1 5 25 15 30 ns /cas to /ras precharge time t crp 5 5 ns row addre ss set - up time t asr 0 0 ns row address hold time t rah 10 10 ns column address set - up time t asc 0 0 ns column address hold time t cah 8 1 0 ns column address hold referenced to /ras t rrh 0 0 ns column address to /ras lead time t ral 25 30 ns read comman d set - up time t rcs 0 0 ns read command hold referenced to /cas t rch 0 0 ns read command hold referenced to /ras t rrh 0 0 ns write command hold time t wch 10 10 ns write command pulse width t wp 10 10 ns write command to /ras lead time t rwl 13 1 5 ns wri te command to /cas lead time t cwl 8 10 ns data - in set - up time t ds 0 0 ns data - in hold time t dh 8 10 ns refresh period t ref 32 32 m s write command set - up time t wcs 0 0 ns /cas to /w delay time t c wd 30 34 ns /ras to /w dela y time t rwd 67 79 ns column address to /w delay time t a wd 42 49 ns /cas precharge to /w delay time t c pwd 4 7 54 ns /cas setup time (/cas - before /ras refresh) t c sr 5 5 ns /cas hold time(/cas - before - /ras refresh) t chr 10 10 ns /ras to /cas precharge time t rp c 5 5 ns access time from /cas precharge t cpa 28 35 ns hyper page mode cycle time t h p c 20 25 ns hyper page mode read - modify write cycle time t h p rwc 47 56 ns /cas precharge time(hyper page cycle) t cp 8 10 ns /ras pulse w idth (hyper page cycle) t rasp 50 200k 60 200k ns /ras hold time from /cas precharge t rhc p 30 35 ns /oe access time t oea 13 15 ns /oe to date delay t oed 13 15 ns output buffer tune off delay time from /o e t oez 3 13 3 15 ns
hanbit hm d4m72d18g url:www.hbe.co.kr - 7 - hanbit electronics co.,ltd. rev. 1.0 (august.2002) /oe command hold time t oeh 13 13 ns output data hold time t doh 10 10 ns output buffer turn off delay from /ras t rez 3 13 3 15 ns output buffer turn off delay from /w t wez 3 13 3 15 ns /w to data delay t wed 15 15 ns /oe to /cas hold time t och 5 5 ns /cas hold time to /oe t cho 5 5 ns /oe precharge time t oep 5 5 ns /w pulse width (hyper page cycle) t wpe 5 5 ns notes 1. an initial pause of 200 m s is requir ed after power - up followed by any 8 /ras - only or /cas - before - /ras refresh cycles before proper device operation is achieved. 2. input voltage levels are v ih (min) and v il (max) are reference levels for measuring timing of input signals. transition times are m easured between v ih(min) and v il(max) and are assumed to be 5ns for all inputs. 3. measured with a load equivalent to 1ttl loads and 100pf 4. operation within the t rcd(max) limit insures that t rac(max) can be met. t rcd(max) is specified as a reference point only . if t rcd is greater than the specified t rcd(max) limit, then access time is controlled exclusively by t cac . 5. assumes that t rcd 3 t rcd(max) 6 .this parameter defines the time at which the output achieves the open circuit condition and is not referenced to v o h or v ol . 7 . t wcs , t rwd , t cwd and t awd are non restrictive operating parameter. they are included in the data sheet as electrical characteristic only. if t wcs 3 twcs(min) the cycle is an early write cycle and the data out pin will remain high im pedance for the duration of the cycle the data output will contain the data read from the selected address . if neither of the above conditions are satisfied, the condition of the data out is indeternimated. 8 . either t rch or t rrh must be satisfied for a re ad cycle. 9 . operation within the t rad(max) limit insures that t rac(max) can be met. t rad(max) is specified as a reference point only. if t rad is greater than the specified t rad(max) limit. then access time is controlled by t aa . 10. if /ras goes to hig h before /cas high going, the open circuit condition of the output is achieved by /cas high going. if /cas goes to high before /ras high going, the open circuit condition of the output is achieved by /ras high going. 11. t asc 3 6ns
hanbit hm d4m72d18g url:www.hbe.co.kr - 8 - hanbit electronics co.,ltd. rev. 1.0 (august.2002) timing diagrams timing waveform of read cycle timing waveform of write cycle (early write) /ras /cas a /w /oe dq /ras /cas a /w /oe dq
hanbit hm d4m72d18g url:www.hbe.co.kr - 9 - hanbit electronics co.,ltd. rev. 1.0 (august.2002) t iming waveform of write cycle ( /oe controlled write) note : dout = open read modify write cycle /ras /cas a /w /oe dq /ras /cas a /w /oe dq
hanbit hm d4m72d18g url:www.hbe.co.kr - 10 - hanbit electronics co.,ltd. rev. 1.0 (august.2002) hyper page read cycle hyper page write cy cle (early write) /ras /cas a /w /oe dq /ras /cas a /w /oe dq
hanbit hm d4m72d18g url:www.hbe.co.kr - 11 - hanbit electronics co.,ltd. rev. 1.0 (august.2002) hyper page read modify write cycle hyper page read and write mixed cycle /ras /cas a /w /oe dq /ras /cas a /w /oe dq
hanbit hm d4m72d18g url:www.hbe.co.kr - 12 - hanbit electronics co.,ltd. rev. 1.0 (august.2002) /ras only refresh cycle note: /w,/oe,din = don't care dout = open /cas before /ras refresh cycle note: /oe, a = don't care /ras /cas a /ras /cas a dq
hanbit hm d4m72d18g url:www.hbe.co.kr - 13 - hanbit electronics co.,ltd. rev. 1.0 (august.2002) hidden refresh cycle ( read) hidden refresh cycle ( write ) note: dout = open /ras /cas a /w /oe dq /ras /cas a /w /oe dq
hanbit hm d4m72d18g url:www.hbe.co.kr - 14 - hanbit electronics co.,ltd. rev. 1.0 (august.2002) /cas before /ras refresh counter test cycle /w /oe dq /w /oe dq /w /oe dq read cycle /ras /cas a write cycle read - modify - write
hanbit hm d4m72d18g url:www.hbe.co.kr - 15 - hanbit electronics co.,ltd. rev. 1.0 (august.2002) /cas before /ras self refresh cycle note : /oe, a = don t care test mode in cycle note: /oe, a = don't care /ras /cas dq /w /ras /cas /w dq
hanbit hm d4m72d18g url:www.hbe.co.kr - 16 - hanbit electronics co.,ltd. rev. 1.0 (august.2002) pack aging information unit:mm (front view) o r dering information part number density org. package component number vcc mode speed hmd4m72d18g - 5 32mbyte x 72 168 pin - dimm 18ea 5v fp 50ns hmd4m72d18g - 6 32mbyte x 72 168 pin - dimm 18ea 5v fp 60ns 3.69 mm max 1.2 7 0. 1 mm 0.25 mm max min 2.54 mm 1.27 mm gold : 1.0 0mm

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